松下FS2鏡頭特點

光學(xué)變焦 3倍

廣角鏡頭 否

長焦鏡頭 否

等效于35mm尺寸 35-105

鏡頭說明 5.8-17.4mm

近拍距離 5cm

光圈大小 F2.8-F5.0

感 光 度 自動，100,200,400,800,1250,3200

高感光度 是

變焦方式 電子

伸縮鏡頭 是

對焦方式 自動對焦

記錄媒介 SD/SDHC卡

記錄容量 內(nèi)置27M內(nèi)存

文件格式 JPEG

電池類型 專用鋰電池

續(xù)航能力 一次性充滿電的情況下可拍攝約350張照片

顯示屏尺寸 2.5英寸

像素及類型 11.5萬像素TFT LCD

可旋轉(zhuǎn)液晶屏 否

機(jī)身類型 消費數(shù)碼相機(jī)

手動操作 部分手動功能

感光元件 CCD

傳感器尺寸 1/2.5英寸

總像素數(shù) 738萬

有效像素 720萬

最高分辨率 3072*2304

圖像分辨率 3072×2304,3072×2048,3072×1728像素

外形設(shè)計 黑色,銀色,粉紅色

外形尺寸 94.1×51.4×24.2mm

產(chǎn)品重量 125g

輕巧機(jī)身 是

時尚超薄 否

大屏幕LCD 否

閃光類型 內(nèi)置

支持熱靴 否

閃光模式 自動,強(qiáng)制,關(guān)閉,防紅眼,慢速同步,防紅眼 慢速同步

自拍功能 支持

動態(tài)拍攝 支持不間斷有聲短片拍攝功能,848×480@30/15fsp,640×480@30/15fsp,320×240@30/15fsp

錄音/音頻系統(tǒng) 支持

場景模式 肖像,風(fēng)景,運動,海灘,雪景,聚會,植物,夜晚風(fēng)景,夜晚肖像

防紅眼 支持

防抖性能 光學(xué)防抖

曝光模式 全自動曝光,程序自動曝光

曝光補(bǔ)償 -2.0EV - 2.0EV,1/3EV級調(diào)節(jié)

曝光測量 中央重點測光

白平衡調(diào)節(jié) 自動,預(yù)置:晴天,陰天,白熾燈,熒光燈

快門速度 60-1/2000秒

數(shù)據(jù)接口 USB2.0

視頻接口 AV接口

發(fā)布日期 2007年06月

面部識別 支持

Wi-Fi功能 不支持

位于美國俄勒岡州Lake Oswego的First Silicon Solutions(FS2)的公司是MIPS Technologies全資子公司。FS2公司專門致力于芯片知識產(chǎn)權(quán)(IP)、設(shè)計服務(wù)和針對SoC、SOPC、FPGA、ASSP和ASIC器件的編程、測試、調(diào)試和嵌入式跟蹤片上儀器(OCI)的開發(fā)工具。

FS2公司的OCI技術(shù)可提供深度的、針對SoC內(nèi)部工作的、覆蓋整個系統(tǒng)的能見度，是實現(xiàn)成功設(shè)計和加速上市的關(guān)鍵。FS2從1999年起就與MIPS Technologies及其客戶密切合作，針對MIPS-Based(tm)核心，開發(fā)尖端的系統(tǒng)除錯與程序追蹤技術(shù)。這項合作關(guān)系后來更延伸至PDtrace(tm)（Program and Data Trace）芯片內(nèi)部與外部的追蹤系統(tǒng)開發(fā)，并應(yīng)用在MIPS32(r) 4KE(tm)、MIPS32 24K(r)、以及MIPS32 24KE(tm)等系列的處理器核心。

此外，F(xiàn)S2還推出System Navigator以協(xié)助業(yè)者針對系統(tǒng)進(jìn)行開發(fā)與除錯，同時FS2亦提供Logic Navigator(tm)系列IP方案與相關(guān)工具，針對涵蓋整個系統(tǒng)的先進(jìn)處理器總線進(jìn)行分析作業(yè)。

FS2仿真器ISA-ACTEL51

In-Target System Analyzer for

Actel Core8051? Microcontroller Core

ISA-ACTEL51專為 ACTEL51 設(shè)計，采用FS2公司獨有的 On-Chip Instrumentation（芯片級在線調(diào)試儀；OCI）和調(diào)試器，通過Actel 的FlashPro Lite 實現(xiàn)目標(biāo)連接，并具有四個硬件執(zhí)行斷點、無限的軟件斷點，以及可選的觸發(fā)器和追蹤功能。

FS2 產(chǎn)品與Actel 產(chǎn)品的緊密配合，能讓使用FS2 之 OCI 工具開發(fā)以Actel Core8051 為基礎(chǔ) FPGA 系統(tǒng)的客戶，大幅縮短設(shè)計周期和降低開發(fā)成本。Keil IDE 可與FS2 的工具完美結(jié)合。

特點

· 支持 bank switching

· 可讀寫全部處理器寄存器, SFRs, program memory 和 data memory

· Go, halt processor run control

· 步執(zhí)行匯編或C 指令

· 無限制軟斷點設(shè)置

· 可下載 binary, Intel Hex或OMF51

· 可達(dá)4 硬件執(zhí)行斷點

· 跟蹤窗口可以顯示匯編、C或混合顯示

· 在源碼窗口中可設(shè)置、軟硬件斷點

Logic NavigatorTM for Actel FPGAs

Logic Analyzer and Debug Tool for Actel Programmable Logic

專為Actel FPGAs設(shè)計。

1、特點：

· 基于FS2 OCI技術(shù)跟蹤和觸發(fā)Actel FPGA 的信號分析

· 用戶可在Actel ProASIC, ProASIC(PLUS), MX, SX,和AX devices配置任意節(jié)點的邏輯分析

· 支持各個級別的觸發(fā)

· 可存儲出發(fā)條件

· 圖形化用戶界面可通過波形或文本輸出

· 命令行Tcl/tk 指令接口

· 可配置的跟蹤和觸發(fā)的優(yōu)化選擇

· 通過 Actel FlashPro 或FlashPro Lite 和目標(biāo)板連接

· OCI 發(fā)生器迅速產(chǎn)生配置 OCI 邏輯塊選項并且可以產(chǎn)生實例代碼。

· 分析達(dá)4096個節(jié)點

· 可達(dá)32個可選的外部觸發(fā)接口

2、 System Navigator for Nios II

System Navigator Products for Nios II Embedded Processors

專為Nios II設(shè)計，采用FS2公司獨有的 On-Chip Instrumentation（芯片級在線調(diào)試儀；OCI）技術(shù)的調(diào)試器

特點 Nios II套件 SNAV-NIOS II-USBProbe SNAV-NIOS II-ETHProbe ISA-NIOS II/T Probe

執(zhí)行斷點數(shù) 2 4 4 4

數(shù)據(jù)/周期斷點 2 4 4 4

跟蹤深度 16 frames Unlimited Unlimited Unlimited (on- chip)

128K frames (off-chip)

數(shù)據(jù)/總線周期跟蹤 No Yes Yes Yes

性能分析 No Yes Yes Yes

跟蹤時間標(biāo)記 No NO NO Yes

主機(jī)連接方式 USB 1.1 USB 2.0 USB 2.010/100 Ethernet USB 1.1 / EPP

觸發(fā) No NO NO Yes

目標(biāo)連接方式　 JTAG JTAG JTAG Mictor-38

離線跟蹤 No NO NO Yes

多核支持 No Yes Yes Yes3、 System Navigator for AMD Alchemy?　Processors

System Navigator tools for

AMD Alchemy Solutions Au1500? and Au1550? Processors

支持AMD芯片的獨特特點，對AMD Alchemy Au1500? 和 Au1550? 處理器深度跟蹤調(diào)試。擴(kuò)展調(diào)試支持 Windows 和 Linux下的 GDB/Insight調(diào)試。低成本下，優(yōu)秀的源碼級調(diào)試。同時也支持圖形界面下直觀方便的Mentor Graphics code|lab和XRAY debuggers 以及Viosoft embedded Linux Arriba 調(diào)試?？赏ㄟ^USB或網(wǎng)口與主機(jī)通訊。

特點：

利用OCI技術(shù)調(diào)試

·支持AMD Alchemy Au1500 和 Au1550 處理器和開發(fā)板，也支持所有 MIPS 4K?, 4KE?, 4KS?, M4K?, 5K?, 20K?, 24K?, and 25K? cores

·支持多樣的源碼級調(diào)試環(huán)境

·通過SDBBP指令可以無限制設(shè)置斷點

·單步執(zhí)行匯編和C代碼

·讀寫全部CPU寄存器

· 無論CPU停止或運行都可讀寫內(nèi)存

· MIPS標(biāo)準(zhǔn)的硬件斷點(EJTAG version 2.51 or later)

·支持FLASH 編程

·控制CPU運行

·通過JTAG功能底層調(diào)試

·單線匯編和反匯編

·支持TCL./TK腳本語言的命令行接口

·包括MDI調(diào)試規(guī)范的2進(jìn)制軟件接口4、 System Navigator for AMD Geode?　GX and LX Processors

支持處理器：

AMD Geode? GX 466@0.9W processor

AMD Geode? GX 500@1.0W processor

AMD Geode? GX 533@1.1W processor

AMD Geode? LX 700@0.8W processor

AMD Geode? LX 800@0.9W processor

AMD Geode? LX 900@01.5W processor

特點：

·在 Geode GX和Geode LX 處理器利用On-Chip Instrumentation (OCI?) 調(diào)試擴(kuò)展

·讀寫CPU 寄存器, MSRs, 內(nèi)存 和I/O

·控制CPU運行

·單步執(zhí)行匯編指令

·無限的軟件斷點

·標(biāo)準(zhǔn)的片上跟蹤和可選的離片跟蹤

·片上跟蹤深度達(dá)128 x 64-bit幀

·離片跟蹤深度達(dá)64K x 64-bit 幀 (可選)

·支持系統(tǒng)管理模式,

·單步通過實模式到保護(hù)模式過渡直到監(jiān)控所有的所有寄存器更新

·支持Flash編程

·用調(diào)試寄存器執(zhí)行硬件斷點

·可在觸發(fā)窗口設(shè)置復(fù)雜觸發(fā)

·復(fù)雜觸發(fā)可監(jiān)控地址和周期類型

·單行匯編和反匯編

·跟蹤窗口全面執(zhí)行跟蹤

·源碼窗口可執(zhí)行: go; halt; goto cursor; step over/into call

·源碼窗口下能夠設(shè)置和清除軟硬件斷點

·包括GNU-based GDB 源碼級程序調(diào)試

· Windows CE Platform Builder 和 在 Windows XP/XPE WinDbg 內(nèi)核級調(diào)試

·支持TCL./TK腳本語言的命令行接口5、System Navigator for Turbo 186 Cores：　System Navigator tools for VAutomation Turbo186 Core and

Lantronix DSTni-LX / DSTni-EX Processors

低成本下，優(yōu)秀的源碼級調(diào)試工具?？蛇x的圖形化界面，直觀方便?？赏ㄟ^USB或網(wǎng)口與主機(jī)通訊。

特點：

· 控制CPU運行

· 單步執(zhí)行匯編指令

· 無限的軟件斷點

· 支持Flash編程

· 用調(diào)試寄存器執(zhí)行硬件斷點

· 支持C或匯編語言

· 源碼窗口能夠顯示C語言或混合顯示

· 源碼窗口可提供運行控制

· 源碼窗口能夠設(shè)置或清除軟硬件斷點

· 源碼窗口允許選擇全局或局部變量并增加到變量窗口中

· 觸發(fā)窗口可設(shè)置復(fù)雜觸發(fā)

· 標(biāo)準(zhǔn)TCL./TK腳本語言的命令行接口

System Navigator for MIPS：

System Navigator tools for

MIPS Technologies MIPS32? and MIPS64? Cores

提供很多功能例如硬件觸發(fā)器、跟蹤邏輯分析在線仿真。

通過14針EJTAG連接目標(biāo)板，可通過網(wǎng)口、和usb.或并口連接主機(jī)，支持Mdi源碼級調(diào)試

軟件斷點

硬件事件識別

Mips芯片包含可配置硬件斷點的，可達(dá)到15個指令斷點執(zhí)行虛擬地址的識別。

只有當(dāng)特殊事件被激活，所有的斷點都可以禁止被Asid打破的斷點。觸發(fā)事件可以用于跟蹤的篩選。

靈活的內(nèi)外部程序和數(shù)據(jù)的選擇

跟蹤可以在片上或片下捕獲。內(nèi)部跟蹤深度可以從16到16k字節(jié)。當(dāng)源碼只有程序分支被存儲

特點

利用OCI技術(shù)調(diào)試

支持mips芯片

支持基于mips sde 工具鏈的gun,mentor 圖形開發(fā)工具和xray以及voisoft

要求ejtag2.5 或以上

標(biāo)準(zhǔn)的片上跟蹤和離片跟蹤

片上跟蹤深度可達(dá)1M64BIT字

實時的PC執(zhí)行跟蹤載入、存儲地址，和數(shù)據(jù)跟蹤

通過觸發(fā)器可以切換跟蹤狀態(tài)

Off-chip trace up to 64K 64-bit words

通過SDBBP指令可以無限制設(shè)置斷點

單步執(zhí)行匯編和C代碼

讀寫全部CPU和CP0寄存器

支持MIPS標(biāo)準(zhǔn)的硬件斷點

支持FLASH 編程

支持多核

控制CPU運行

底層調(diào)試通過JTAG功能

單線匯編和反匯編

支持TCL./TK腳本語言的命令行接口

包括MDI調(diào)試規(guī)范的2進(jìn)制軟件接口

源碼級調(diào)試直觀易用

FS2仿真器Navigator IDE for MIPS：

Eclipse-based Navigator debugger IDE for

MIPS Technologies MIPS32? and MIPS64? Cores

與Eclipse兼容的圖形化MIPS核開發(fā)調(diào)試環(huán)境8、ABS of the Benefits of MIPS PDtrace?

FS2 System Navigator JTAG ProbesMIPS? Software Toolkit

MIPS? SDE GNU based toolchain, MIPSsim(TM) Instruction Set Simulator,

MIPS? DSP Library and Technical Support

System Navigator for CAST8051

System Navigator tools for

CAST 8051 Synthesizable Microcontroller Cores

支持CPU:

（CAST R8051XC, R80515, R8051, C8051 cores）

兼容開發(fā)環(huán)境

Keil μVision3 software

12、SNAV-HT80C51

System Navigator tools for Handshake Solutions

HT80C51 and HT80C51MX Clockless Microcontroller Cores

支持CPU: HT80C51 和 HT80C51MX

兼容開發(fā)環(huán)境：Keil 系列

System Navigator for Mentor M8051EW

System Navigator tools for Mentor M8051EW

Synthesizable Microcontroller Cores

System Navigator for Philips LPC952

System Navigator for

Philips LPC952 Microcontroller

FS2仿真器ISA-JAZZ System Analyzer

In-Target System Analyzer for Improv Systems Jazz DSP Processor Cores

The ISA-JAZZ In-Target System Analyzer is designed to support the special features and integrated peripherals of the Jazz processor family. It works with the Improv Systems Jazz Standard Tool Suite and provides a JTAG interface to the family DSP processors.

The ISA-Jazz System Analyzer supports JTAG-based debugging for Improv Systems Jazz cores with COOL-Jazz debugging extensions. It features complete run control over one or more Jazz DSP processor cores and enables you to access and modify registers, memory, and I/O. The JTAG based probe works with the Improv Systems tool suite debugger for a graphical user interface. This provides a powerful multi core debug tool for Jazz cores with advanced features at a competitive price.

Key Features

· Read-write all processor registers, memory, and I/O ports

· Go and halt processor run control

· Single step by assembly or C source instruction

· Set hardware and software breakpoints

· Load binary, hex, S-records file formats

· Supports multiple Jazz cores on JTAG chain

· Supports flash programming

· Trigger-in/out signals

· Supported by Jazz debugger and development tool suite

FS2仿真器ISA-ZSP500

In-Target System Analyzer for LSI Logic ZSP500 DSP Core

The In-Target System Analyzer supports the LSI Logic ZSP?500 synthesizable DSP core. To learn more about the ZSP500 core, visit the web site at www.zsp.comThe ZSP500 core is available with optional FS2 On-chip Instrumentation (OCI?) IP with trace and triggering features for faster system debug and testing. It provides unique performance analysis features that make it easier to find execution bottlenecks and improve performance.

The FS2 system analyzer probe connects to the ZSP500 target system using a 14-pin JTAG connector or 38-pin Mictor cable (with off-chip trace system). The system runs on a Windows?98/NT/2000/XP PC over an IEEE-1284 EPP/bi-directional parallel port.

Key Features

· Supports LSI Logic ZSP500 DSP core

· Features FS2 On-Chip Instrumentation (OCI) technology

· On-chip trace (standard), off-chip trace, or both

· Supports 24-bit addressing

· Real-time PC execution trace

· Load/store address trace

· Detailed Execution Profiling Trace mode for measuring CPU resource utilization

· Point-to-point timing to assist in code performance optimization

· Trace can be gated on/off by on-chip triggers

· Scalable internal trace depth

· External trace port width and speed selectable

· Max trace depth: on-chip 1024 x 64-bit words, off-chip 64K x 64-bit words

· Unlimited software breakpoints

· ZSP hardware breakpoints

· Go, halt processor run control

· Read-write all general registers and control registers

· Supports multiple cores and mixed RISC/DSP development

· Host binary software interface adheres to MDI specification

· Command-line interface window with Tcl scripting

FS2仿真器Sitka Development Board

Evaluation and Development Board for Synopsys DesignWare PCI Express IP

The Sitka development and evaluation board was jointly developed by Synopsys and First Silicon Solutions for the Synopsys DesignWare PCI Express IP. The board functions as a standard PCIe add-in card for systems running either the Windows or Linux operating systems.

The Sitka board contains two large Xilinx Virtex-4 FPGA's which allow you to combine your design with the DesignWare PCI Express IP enabling you to test and debug your PCI Express application in hardware. The FPGA's support partitioning of large designs by providing 272 I/O pins between the two FPGA's. These I/O's can be configured for operation up to 1Gpbs point-to-point to provide high throughput data transfers or grouped into sets of unidirectional channels. The FPGA's are configured with on-board ROM that can hold two or more configurations depending on the bitfile compression that is used.

The board enables testing the DesignWare PCI Express IP with multiple PHYs for maximum flexibility in choosing the PHY for the final design. For testing purposes, you can use the built-in FX60 PHY connecting directly to specific connectors like the PCIe interface and SATA drives or through the 360-pin expansion connector. In addition to using the built-in FPGA PHYs, you can use daughter cards connected to the Sitka board via two different connector locations, including the PCI Express Standard PIPE_C (PHY Interface PCI Express Architecture Connector). The Sikta board can run any combination or all of these interfaces simultaneously.

The Sitka board, when used in conjunction with the industry standard DesignWare PCI Express IP enables faster and easier verification of the design in hardware.

Key Features

· PCIe x8 board edge connector (adaptors plug into a PCIe x1 or x4 PC slot)

· PCI Express PHY Interface for PCI Express Architecture Connector (PIPE_C) enables PHY testing through a PHY daughter card

· PMA Interface connector for use with Synopsys PHY daughter cards

· 2 SATA drive connectors

· 2 SFP connector sites for Gigabit Ethernet (GigE)

· 2 XENPAK connector sites for XAUI (adaptors for additional SATA or SFP)

· Cup connectors for TI power source modules

· 2 Xilinx JTAG connectors, one each wired to FX60 and LX100 for using the ChipScope Pro debugger

· Xilinx XC4VFX60-10FF1152

· Xilinx XC4VLX100-10FF1513

· 3 XCF32P configurable FLASH devices for 2 selectable Xilinx image loads

· 2 independent Xilinx-approved clock sources for the Rocket IO (PCIe and SATA)

· 2 clock sources for PMA PHY 'H' connector daughter card

· LEDs for board diagnostics

ISA-QMIPS

ISA-Eclipse

FS2 System Analyzers for

QuickLogic? QuickMIPS? ESP Family and

Eclipse? FPGA Devices

ISA-eZ80

In-Target System Analyzer for ZiLOG eZ80 Processor Family

The ISA-eZ80 In-Target System Analyzer is designed to support the special features and integrated peripherals of the eZ80 processor family. It supports the ZiLOG Developer Studio (ZDS) and is integrated with the IAR Embedded Workbench software tools to maximize your productivity.

The system analyzer features complete run control over the eZ80 processor and enables you to access and modify CPU registers, memory, and I/O. FS2's On-Chip Instrumentation (OCI(TM)) debug features built-in to the ZiLOG processors allow FS2 to provide a powerful debug tool with advanced features at a competitive price.

The ISA-eZ80 debugger hardware is contained in a compact chassis that connects to the target system using a 14-pin JTAG connector. The system runs on a Windows? 98/NT/2000 PC over an IEEE-1284 EPP/ECP high-speed parallel port or USB port. The JTAG target interface and high-speed parallel host intface provides typical 8K bytes/sec. loading speeds so you spend more time debugging than waiting for programs to load. A graphical, source level debugger program provides an intuitive, easy to use interface for use with the ZiLOG Developer Studio (ZDS) tools. The system can also be used with the IAR Embedded Workbench debugger interface (sold separately) for complete compatibility with IAR software tools.

IAR Embedded Workbench Interface

IAR Web site

Zilog Web site

Key Features

· Supports ZiLOG eZ80L92, eZ80F91, eZ80F92, eZ80F93, and other processors with available JTAG debug interface

· Read-write all processor registers, memory, and I/O

· Go and halt processor run control

· Trace window with executed assembly and source code

· Single step by assembly or C source instruction

· Unlimited software breakpoints

· Load binary, hex, S-records or COFF (from ZDS) and IAR file formats

· JTAG target and EPP parallel host interface for faster loading

· Flash programming support

· 4 hardware execution breakpoints

· 4 ZDI triggers monitor addrss, address ranges, with option to break on any cycle type

· 4 additional advanced hardware triggers on address, data value, and cycle types, with ranges and masking supported

· Trigger-in/out signals

· Single line assembler and disassembler

· Load code and debug symbols including code, variables, and variable types

· Source level debug from IAR Embedded Workbench interface

· Standalone source debug interface (GUI) supports ZDS tools

FLASH PRO OEM product for Actel ProASIC and ProASICPLUS devices

FPGAView? Software

Software for Configuring and Debugging Altera and Xilinx FPGA Devices with Tektronix Logic Analyzers

The FPGAView? software is a PC Windows-based program

FS2 BUS NAVIGATOR?

On-chip FS2 Bus Navigator? Solutions for AMBA, OCP,

and Sonics SiliconBackplane Bus Systems

The FS2 Bus Navigator? is used for monitoring signal activity and for debugging complex bus/system interactions in System-on-Chip designs. It allows the user to capture bus activity in real-time and display critical information for analysis on a host PC.

The system consists of an On-chip Instrumentation (OCI?) synthesizable logic block, a JTAG hardware probe, and PC based software for controlling probing and analysis. The OCI passively captures bus activity, buffers it using on-chip RAM, and transfers the collected data off-chip via a JTAG port to the external JTAG probe. The host PC controls the trace collection process and provides captured bus history to the user with an easy-to-use graphical interface. The system runs on a Windows? 2000/XP PC over a USB 2.0 or optional 10/100 Ethernet port. It provides a comprehensive debug tool for complex SoC bus designs at a competitive price.

Key Features

· Captures bus activity in real-time

· Available for AMBA, OCP, and Sonics SiliconBackplane buses

· Captures bus signals and additional user-defined inputs attached to other nodes in the SOC

· Bus clock mode trace stores signals on every clock

· Bus transfer mode aligns bus transfers and response phases for single event triggering using combinations of address, data, and control

· Filtering of wait and idle state cycles in bus transfer mode

· Trace storage qualifiers; single cycle, start or stop trace on any trigger, counter, and state sequencer condition

· Configurable for user defined number of Masters

· Trace buffer stores bus cycles or bus transfers based on RAM memory size

· Up to 16 user defined triggers recognize combinations of 1, 0, X, signal values

· Sequential event monitoring using cascadable trigger states (2 to 16 states)

· Two 32-bit event counter/timers

· Trigger conditions include bus and user defined signals, Event counter/timer value, and Trigger state

· Actions include Trigger, Trace control (start, stop, single), Trig Out control (pulse, assert, negate), Counter control (increment, start, stop, clear), and Goto state

· Trigger position variable in 1/512 increments of trace depth

· User difinable timestamp records duration of each trace frame from the start of trace, displayable as absolute or delta times

· Automatic trace clock frequency measurement allows displaying frame durations in either nanoseconds or clocks

· Multiple external trigger in/out with configurable logic levels

· Easy-to-use graphical software interface with state views and waveform views of data

· Symbolic lookup and signal value naming support for ease of viewing and analysis

· Optional VCD format export for integration with simulation environments

Cadence Emulation Tools Support

Integrating Instrumentation Tools into System-Level Verification Flows. This is a PowerPoint presentation.2100433B