Altera系列FPGA芯片IP核詳解

Altera IP核是面向Altera可編程邏輯門(mén)陣列(FPGA)芯片優(yōu)化的、實(shí)現(xiàn)電子設(shè)計(jì)中常用功能的封裝模塊。本書(shū)以Altera公司的Arria、HardCopy、Cyclone和Stratix系列FPGA芯片為基礎(chǔ)，詳細(xì)介紹各類(lèi)IP核的特點(diǎn)、接口信號(hào)以及功能描述，并對(duì)部分IP核的信號(hào)時(shí)序進(jìn)行分析。全書(shū)共分9章，首先介紹在Quartus II軟件中生成和使用Altera IP核方法，然后按照IP核的功能分類(lèi)詳細(xì)介紹用于數(shù)學(xué)運(yùn)算、數(shù)據(jù)存儲(chǔ)、數(shù)字信號(hào)處理(DSP)、通信和網(wǎng)絡(luò)、圖像處理、輸入/輸出、通信接口以及FPGA調(diào)試驗(yàn)證的Altera IP核。

Altera系列FPGA芯片IP核詳解基本信息

書(shū)名 Altera系列FPGA芯片IP核詳解 類(lèi)型 計(jì)算機(jī)與互聯(lián)網(wǎng)
出版日期 2014年1月1日 語(yǔ)種 簡(jiǎn)體中文, 英語(yǔ)
品牌 電子工業(yè)出版社 作者 劉東華
出版社 電子工業(yè)出版社 頁(yè)數(shù) 623頁(yè)
開(kāi)本 16

內(nèi)容簡(jiǎn)介

本書(shū)詳細(xì)講述了Altera FPGA的IP核，使讀者更加深入地理解FPGA的開(kāi)發(fā)和應(yīng)用

作者簡(jiǎn)介

劉東華，男，內(nèi)蒙古人，博士，副教授，2002年畢業(yè)于國(guó)防科技大學(xué)，獲信息與通信工程專(zhuān)業(yè)博士學(xué)位，2004年入中國(guó)科學(xué)院計(jì)算技術(shù)研究所計(jì)算機(jī)科學(xué)與技術(shù)博士后流動(dòng)站，2006年出站。曾參與完成科研項(xiàng)目十余項(xiàng)，發(fā)表相關(guān)學(xué)術(shù)論文二十余篇，主講本科生課程《信息論與編碼》、研究生課程《糾錯(cuò)編碼》和博士生選修課《高級(jí)編碼技術(shù)研討》，主要研究方向?yàn)樾畔⒄撆c信道編碼。

Altera系列FPGA芯片IP核詳解造價(jià)信息

市場(chǎng)價(jià) 信息價(jià) 詢(xún)價(jià)
材料名稱(chēng) 規(guī)格/型號(hào) 市場(chǎng)價(jià)
（除稅）		 工程建議價(jià)
（除稅）		 行情 品牌 單位 稅率 供應(yīng)商 報(bào)價(jià)日期
芯片卡 CA-EI-C品種:ID卡片; 查看價(jià)格 查看價(jià)格

霍尼韋爾

 個(gè) 13% 石家莊冠旭商貿(mào)有限公司
芯片卡 CA-MS-C品種:系統(tǒng)調(diào)試卡;型號(hào):Mifare-1; 查看價(jià)格 查看價(jià)格

霍尼韋爾

 個(gè) 13% 石家莊冠旭商貿(mào)有限公司
控制器組網(wǎng)芯片 查看價(jià)格 查看價(jià)格

套 13% 四川久遠(yuǎn)智能監(jiān)控有限責(zé)任公司昆明辦事
滴膠卡ID芯片 說(shuō)明:100張起售 查看價(jià)格 查看價(jià)格

宏卡

 瓶 13% 沈陽(yáng)宏卡科技開(kāi)發(fā)有限公司
滴膠卡IC復(fù)旦芯片 說(shuō)明:100張起售 查看價(jià)格 查看價(jià)格

宏卡

 瓶 13% 沈陽(yáng)宏卡科技開(kāi)發(fā)有限公司
EM芯片,帶噴碼/IC原裝飛利浦芯片 ID鑰匙扣卡類(lèi)別:十一、讀卡器系列;說(shuō)明:S50; 查看價(jià)格 查看價(jià)格

凱利杰

 個(gè) 13% 深圳市凱利杰電子科技有限公司
飛利浦芯片 KAD-S50品種:IC卡; 查看價(jià)格 查看價(jià)格

科視達(dá)

 個(gè) 13% 石家莊云視盾電子科技有限公司
芯片卡（白卡） 品種:IC卡片;系列:原裝S50 查看價(jià)格 查看價(jià)格

和

 張 13% 深圳市建和智能卡技術(shù)有限公司長(zhǎng)沙辦事處
材料名稱(chēng) 規(guī)格/型號(hào) 除稅
信息價(jià)		 含稅
信息價(jià)		 行情 品牌 單位 稅率 地區(qū)/時(shí)間
自動(dòng)洗片機(jī) 查看價(jià)格 查看價(jià)格

臺(tái)班 韶關(guān)市2010年8月信息價(jià)
X光片脫水烘干機(jī) ZTH-340 查看價(jià)格 查看價(jià)格

臺(tái)班 韶關(guān)市2010年8月信息價(jià)
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價(jià)格 查看價(jià)格

臺(tái)班 汕頭市2011年3季度信息價(jià)
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價(jià)格 查看價(jià)格

臺(tái)班 汕頭市2011年2季度信息價(jià)
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價(jià)格 查看價(jià)格

臺(tái)班 廣州市2011年1季度信息價(jià)
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價(jià)格 查看價(jià)格

臺(tái)班 汕頭市2010年3季度信息價(jià)
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價(jià)格 查看價(jià)格

臺(tái)班 汕頭市2010年2季度信息價(jià)
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價(jià)格 查看價(jià)格

臺(tái)班 廣州市2010年1季度信息價(jià)
材料名稱(chēng) 規(guī)格/需求量 報(bào)價(jià)數(shù) 最新報(bào)價(jià)
（元）		 供應(yīng)商 報(bào)價(jià)地區(qū) 最新報(bào)價(jià)時(shí)間
系統(tǒng)芯片 :(Vcc/Vdd)1.81V - 2V數(shù)據(jù)轉(zhuǎn)換器A/D: 16x12b振蕩器類(lèi)型:內(nèi)部工作溫度:-40°C - 125°C(TA)|20個(gè) 1 查看價(jià)格 深圳市芯航國(guó)際電子有限公司 全國(guó)   2022-08-09
RFID芯片 工作頻率:915±45MHz|10600個(gè) 1 查看價(jià)格 深圳市奧斯達(dá)電子有限公司 全國(guó)   2018-08-21
信息芯片 DS1990A-F5|5926臺(tái) 1 查看價(jià)格 上海格瑞特科技實(shí)業(yè)有限公司 上海  上海市 2015-07-15
DSP芯片卡 1、DSP資源擴(kuò)展卡2、含2個(gè)DSP芯片3、處理芯片運(yùn)算能力不劣于800MHz|1塊 1 查看價(jià)格 廣州市熹尚科技設(shè)備有限公司 全國(guó)   2020-05-11
MI高頻芯片房卡 1.名稱(chēng):MI高頻芯片房卡2.參數(shù):M1高頻芯片卡,房卡智能化使用第十扇區(qū)|1000張 1 查看價(jià)格 全國(guó)  
儀表芯片 HY6264 稱(chēng)重?cái)?shù)據(jù)儲(chǔ)存|8163塊 1 查看價(jià)格 廣東華普電器實(shí)業(yè)集團(tuán)有限公司 廣東  佛山市 2015-11-10
儀表芯片 74HC573|8163塊 1 查看價(jià)格 廣東華普電器實(shí)業(yè)集團(tuán)有限公司 廣東  佛山市 2015-07-23
儀表芯片 TC7652CPD A/D運(yùn)放集成|8556塊 1 查看價(jià)格 廣東華普電器實(shí)業(yè)集團(tuán)有限公司 廣東  佛山市 2015-05-12

Altera系列FPGA芯片IP核詳解常見(jiàn)問(wèn)題

  • DSP、MCU、CPLD、ARM、FPGA芯片的區(qū)別

    1，單片機(jī)小型電腦處理器，最小可以到8個(gè)腳，價(jià)格便宜，最便宜2塊錢(qián)2，PLC可變邏輯控制器，主要用在工業(yè)控制，里面是類(lèi)似一個(gè)加強(qiáng)的單片機(jī)。對(duì)輸入輸出均有做處理例如抗干擾，增加帶負(fù)載驅(qū)動(dòng)能力3，DSP ...

  • LED芯片 封裝

    1. LED的封裝的任務(wù) 是將外引線(xiàn)連接到LED芯片的電極上，同時(shí)保護(hù)好LED芯片，并且起到提高光取出效率的作用。關(guān)鍵工序有裝架、壓焊、封裝。2. LED封裝形式 LED封裝形式可以說(shuō)是五花八門(mén)，主要...

  • tda lm系列大功率功放芯片

    TDA7388 7389 4X45WTDA7293 7294 100WLM3876 3886 68WLM4766 2X40WLM4780 2X60W

Altera系列FPGA芯片IP核詳解文獻(xiàn)

基于FPGA的音頻編解碼芯片控制器設(shè)計(jì) 基于FPGA的音頻編解碼芯片控制器設(shè)計(jì)

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摘要 現(xiàn)如今隨著可編程邏輯器件及相關(guān)技術(shù)的不斷發(fā)展和完善， 其技術(shù)在現(xiàn)代 電子技術(shù)領(lǐng)域表現(xiàn)出的明顯技術(shù)領(lǐng)先性， 具有傳統(tǒng)方法無(wú)可比擬的優(yōu)越性。 近 幾年，嵌入式數(shù)字音頻產(chǎn)品受到越來(lái)越多消費(fèi)者的青睞。在 MP3、手機(jī)等電 子產(chǎn)品中，音頻處理功能已成為不可或缺的重要組成部分， 而高質(zhì)量的音效是 當(dāng)前發(fā)展的重要趨勢(shì)。 數(shù)字語(yǔ)音集成電路與嵌入式微處理器相結(jié)合， 既實(shí)現(xiàn)了系統(tǒng)的小型化、 低 功耗，又降低了產(chǎn)品開(kāi)發(fā)成本，提高了設(shè)計(jì)的靈活性，具有體積小、 擴(kuò)展方便 等諸多特點(diǎn)，具有廣泛的發(fā)展前景。 本設(shè)計(jì)基于 SOPC技術(shù)，利用 Verilog HDL 硬件描述語(yǔ)言開(kāi)發(fā)的基于 FPGA 的音頻編解碼芯片控制器，以實(shí)現(xiàn)對(duì)音頻編解碼芯片 WM8731 的控制。并根 據(jù) Verilog HDL 可移植性和不依賴(lài)器件的特點(diǎn)。經(jīng)過(guò)適當(dāng)?shù)男薷模摽刂破骺?以移植到各類(lèi) FPGA 中，以控制兼容 I2C和 I2S總線(xiàn)

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幾種常用led芯片的比較3528芯片6530芯片1W大功率 幾種常用led芯片的比較3528芯片6530芯片1W大功率

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關(guān)于幾種常用芯片的比較 3528 芯片：?jiǎn)晤w 0.06W，單顆流明 7-9LM 3528 技術(shù)穩(wěn)定成熟， 發(fā)熱量極低， 光衰小， 光色一致性好， 并廣泛應(yīng)用于 LED 電腦顯示器， LED 電視機(jī)背光照明使用。 3528 芯片因?yàn)榱炼雀?，光線(xiàn)柔和，單顆功率低，發(fā)熱量低等特點(diǎn)，完全符合 LED 吸頂燈全 面板光源需求， 全面板光源的應(yīng)用完全彌補(bǔ)了環(huán)形燈管光線(xiàn)不均勻， 中間以及外圍有暗區(qū)的 缺陷，真正實(shí)現(xiàn)了無(wú)暗區(qū)。 5630/6040 芯片：?jiǎn)晤w功率 0.5-0.6W，單顆流明 30-50W 新近出現(xiàn)的封裝模式， 發(fā)光強(qiáng)度及發(fā)熱量介于中功率和大功率之間， 產(chǎn)量低， 光色一致性較 差，主要用于燈泡，射燈，筒燈，天花燈等高密度燈具，光強(qiáng)很強(qiáng)，炫光感強(qiáng)，很刺眼，必 須配獨(dú)立的全鋁散熱器，否則在很短時(shí)間內(nèi)會(huì)出現(xiàn)嚴(yán)重光衰，嚴(yán)重影響燈具壽命。 大功率 1W 芯片：?jiǎn)晤w功率為 1W，單顆流明 80-90

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第1 章 FPGA 架構(gòu)總體設(shè)計(jì) ········································································· 1

1.1 FPGA 芯片研制流程·········································································· 1

1.2 FPGA 架構(gòu)設(shè)計(jì)流程·········································································· 7

1.3 FPGA 規(guī)模和資源劃分 ····································································· 17

1.4 FPGA 中功能模塊劃分 ····································································· 20

本章參考文獻(xiàn) ······················································································ 26

第2 章 FPGA 中時(shí)鐘網(wǎng)絡(luò) ·········································································· 30

2.1 簡(jiǎn)介 ···························································································· 30

2.2 FPGA CDN 建模 ············································································· 33

2.3 時(shí)鐘網(wǎng)絡(luò)設(shè)計(jì)方法 ·········································································· 43

2.4 時(shí)鐘網(wǎng)絡(luò)的靈活性 ·········································································· 48

2.5 路由級(jí)聯(lián) ······················································································ 51

2.6 仿真實(shí)驗(yàn) ······················································································ 55

2.7 時(shí)鐘網(wǎng)絡(luò)熱學(xué)建模 ·········································································· 61

2.8 仿真實(shí)驗(yàn) ······················································································ 62

本章參考文獻(xiàn) ······················································································ 66

第3 章 FPGA 中電源/地線(xiàn)網(wǎng)絡(luò)和漏電流 ······················································· 68

3.1 電源/地線(xiàn)網(wǎng)絡(luò) ··············································································· 68

3.2 IR-DROP 分析與優(yōu)化 ········································································ 71

3.3 漏電流組成 ··················································································· 73

3.4 降低漏電流的方法 ·········································································· 74

3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77

3.6 仿真實(shí)驗(yàn) ······················································································ 81

3.7 不均勻測(cè)試點(diǎn)的IR-DROP 求解 ··························································· 87

3.8 FPGA 電源網(wǎng)絡(luò)IR-DROP 分析 ···························································· 89

本章參考文獻(xiàn) ······················································································ 94

第4 章 FPGA 中可編程邏輯單元 ································································· 98

4.1 基于多路選擇器的邏輯單元 ······························································ 98

4.2 基于四輸入LUT 的可編程邏輯單元的設(shè)計(jì) ·········································· 102

4.3 LUT 的模型與實(shí)現(xiàn) ········································································ 103

4.4 LUT 的輸入數(shù)目K 的確定 ······························································· 106

4.5 進(jìn)位邏輯 ····················································································· 109

4.6 基于查找表結(jié)構(gòu)的FPGA 的不足 ······················································· 115

4.7 AIC 結(jié)構(gòu)邏輯簇 ············································································ 117

4.8 基于AIC 結(jié)構(gòu)FPGA 的邏輯簇 ························································· 120

4.9 面向AIC 的映射工具及結(jié)構(gòu)評(píng)估平臺(tái) ················································ 124

4.10 結(jié)構(gòu)特征匹配的AIC 簇互連優(yōu)化 ···················································· 125

4.11 仿真分析和比較 ·········································································· 131

本章參考文獻(xiàn) ····················································································· 133

第5 章 FPGA 中可編程I/O 模塊 ································································· 136

5.1 可編程I/O 系統(tǒng)結(jié)構(gòu) ······································································ 136

5.2 IOE 中的可編程輸入緩沖器設(shè)計(jì) ······················································· 138

5.3 IOE 中的可編程輸出緩沖器設(shè)計(jì) ······················································· 144

5.4 可編程I/O 的后端版圖設(shè)計(jì)······························································ 156

5.5 高可靠I/O 模塊的后端版圖與測(cè)試 ····················································· 166

5.6 可編程I/O 的供電策略 ··································································· 172

5.7 全芯片IO 的ESD 技術(shù) ··································································· 173

本章參考文獻(xiàn) ····················································································· 179

第6 章 FPGA 中DDR 存儲(chǔ)器接口 ······························································ 182

6.1 DDR SDRAM 芯片的工作原理 ·························································· 182

6.2 FPGA 芯片中DDR 存儲(chǔ)器接口系統(tǒng)設(shè)計(jì) ············································· 184

6.3 DDR 存儲(chǔ)器接口控制器的設(shè)計(jì)和驗(yàn)證 ················································ 191

6.4 延時(shí)鎖相技術(shù) ··············································································· 194

6.5 延時(shí)鎖定環(huán)電路的分析與對(duì)比 ·························································· 196

6.6 數(shù)字延時(shí)鎖定環(huán)電路的性能分析與優(yōu)化 ·············································· 201

6.7 延時(shí)鎖定環(huán)線(xiàn)性模型與穩(wěn)定性分析 ···················································· 205

本章參考文獻(xiàn) ····················································································· 209

第7 章 FPGA 中數(shù)字延時(shí)鎖定環(huán) ································································ 213

7.1 實(shí)現(xiàn)相移的全數(shù)字延遲鎖定環(huán) ·························································· 213

7.2 數(shù)字控制延時(shí)鏈 ············································································ 215

7.3 時(shí)間數(shù)字轉(zhuǎn)換器 ············································································ 220

7.4 雙向移位計(jì)數(shù)器 ············································································ 221

7.5 鑒相器與鎖定邏輯 ········································································· 222

7.6 延遲鎖定環(huán)的版圖設(shè)計(jì) ··································································· 224

7.7 延遲鎖定環(huán)環(huán)路的仿真 ··································································· 224

7.8 芯片的物理實(shí)現(xiàn)與測(cè)試平臺(tái) ····························································· 225

7.9 DDR 接口的數(shù)據(jù)通路的測(cè)試驗(yàn)證 ······················································ 227

7.10 數(shù)字延時(shí)鎖定環(huán)的測(cè)試 ································································· 229

7.11 數(shù)字占空比矯正電路的測(cè)試 ···························································· 232

本章參考文獻(xiàn) ····················································································· 234

第8 章 FPGA 中連線(xiàn)連接盒 ······································································ 236

8.1 引言 ··························································································· 236

8.2 問(wèn)題分析 ····················································································· 237

8.3 利用模擬退火算法優(yōu)化CB 拓?fù)浣Y(jié)構(gòu) ·················································· 241

8.4 實(shí)驗(yàn)及結(jié)果分析 ············································································ 246

8.5 連線(xiàn)開(kāi)關(guān)盒的電路結(jié)構(gòu)設(shè)計(jì)方法 ······················································· 251

本章參考文獻(xiàn) ····················································································· 259

第9 章 FPGA 中互連線(xiàn)段長(zhǎng)度分布 ····························································· 261

9.1 所提優(yōu)化方法的基本思路 ································································ 261

9.2 以面積延時(shí)積最小為目標(biāo)的優(yōu)化 ······················································· 265

9.3 針對(duì)所提優(yōu)化方法的討論 ································································ 268

9.4 設(shè)計(jì)實(shí)驗(yàn) ····················································································· 269

9.5 FPGA 芯片的設(shè)計(jì)實(shí)現(xiàn) ···································································· 270

9.6 芯片的測(cè)試準(zhǔn)備 ············································································ 272

本章參考文獻(xiàn) ····················································································· 275

第10 章 FPGA 中的配置模塊 ···································································· 277

10.1 配置系統(tǒng)的基本組成及特點(diǎn) ···························································· 277

10.2 配置系統(tǒng)的功能需求 ···································································· 279

10.3 配置系統(tǒng)的硬件結(jié)構(gòu)分析 ······························································ 281

10.4 配置碼流協(xié)議的結(jié)構(gòu)及其對(duì)配置系統(tǒng)的影響 ······································· 286

10.5 配置系統(tǒng)總體框架 ······································································· 292

10.6 配置碼流協(xié)議的設(shè)計(jì) ···································································· 297

10.7 配置系統(tǒng)的電路設(shè)計(jì)與實(shí)現(xiàn) ···························································· 300

10.8 配置系統(tǒng)采用的驗(yàn)證工具與方法 ······················································ 305

10.9 配置系統(tǒng)的驗(yàn)證方案與功能點(diǎn)的抽取 ················································ 310

10.10 配置系統(tǒng)功能驗(yàn)證平臺(tái)的設(shè)計(jì) ······················································· 312

10.11 配置系統(tǒng)驗(yàn)證結(jié)果 ······································································ 319

本章參考文獻(xiàn) ····················································································· 324

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本書(shū)以Altera公司的FPGA器件為開(kāi)發(fā)平臺(tái)，采用MATLAB及Verilog HDL語(yǔ)言開(kāi)發(fā)工具，詳細(xì)闡述了數(shù)字濾波器的實(shí)現(xiàn)原理、結(jié)構(gòu)、方法及仿真測(cè)試過(guò)程，并通過(guò)大量工程實(shí)例分析其在FPGA實(shí)現(xiàn)過(guò)程中的具體技術(shù)細(xì)節(jié)。其主要內(nèi)容包括FIR濾波器、IIR濾波器、多速率濾波器、自適應(yīng)濾波器、變換域?yàn)V波器、解調(diào)系統(tǒng)的濾波器設(shè)計(jì)等。本書(shū)思路清晰、語(yǔ)言流暢、分析透徹，在簡(jiǎn)明闡述設(shè)計(jì)原理的基礎(chǔ)上，追求對(duì)工程實(shí)踐的指導(dǎo)性，力求使讀者在較短的時(shí)間內(nèi)掌握數(shù)字濾波器的FPGA設(shè)計(jì)知識(shí)和技能。

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杜勇，四川省廣安市人，高級(jí)工程師。1999年于湖南大學(xué)獲電子工程專(zhuān)業(yè)學(xué)士學(xué)位，2005年于國(guó)防科技大學(xué)獲信息與通信工程專(zhuān)業(yè)碩士學(xué)位。主要從事數(shù)字信號(hào)處理、無(wú)線(xiàn)通信以及FPGA應(yīng)用技術(shù)研究。發(fā)表學(xué)術(shù)論文十余篇，出版《數(shù)字濾波器的MATLAB與FPGA實(shí)現(xiàn)（第2版）》、《數(shù)字通信同步技術(shù)的MATLAB與FPGA實(shí)現(xiàn)》、《數(shù)字調(diào)制解調(diào)技術(shù)的MATLAB與FPGA實(shí)現(xiàn)》等多部著作。

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Altera系列FPGA芯片IP核詳解相關(guān)推薦
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