第1章 設計環(huán)境及開發(fā)平臺介紹 1
1.1 FPGA基礎知識 2
1.1.1 基本概念及發(fā)展歷程 2
1.1.2 FPGA的結構和工作原理 4
1.1.3 FPGA在數(shù)字信號處理中的應用 12
1.2 Altera器件簡介 12
1.3 Verilog HDL語言簡介 15
1.3.1 HDL語言簡介 15
1.3.2 Verilog HDL語言特點 16
1.3.3 Verilog HDL程序結構 17
1.4 Quartus II開發(fā)套件 18
1.4.1 Quartus II開發(fā)套件簡介 18
1.4.2 Quartus II軟件的用戶界面 19
1.5 ModelSim仿真軟件 22
1.6 MATLAB軟件 24
1.6.1 MATLAB軟件介紹 24
1.6.2 MATLAB工作界面 24
1.6.3 MATLAB的特點及優(yōu)勢 25
1.6.4 MATLAB與Quartus的數(shù)據(jù)交互 27
1.7 SystemView軟件 28
1.7.1 SystemView簡介 28
1.7.2 SystemView工作界面 29
1.8 小結—欲善其事先利其器 32
第2章 FPGA數(shù)字信號處理基礎 33
2.1 FPGA中數(shù)的表示 34
2.1.1 萊布尼茲與二進制 34
2.1.2 定點數(shù)表示 35
2.1.3 浮點數(shù)表示 36
2.2 FPGA中數(shù)的運算 40
2.2.1 加/減法運算 40
2.2.2 乘法運算 43
2.2.3 除法運算 44
2.2.4 有效數(shù)據(jù)位的計算 44
2.3 有限字長效應 47
2.3.1 字長效應的產生因素 47
2.3.2 A/D轉換的字長效應 48
2.3.3 系統(tǒng)運算中的字長效應 49
2.4 FPGA中的常用處理模塊 51
2.4.1 加法器模塊 51
2.4.2 乘法器模塊 53
2.4.3 除法器模塊 56
2.4.4 浮點運算模塊 57
2.5 小結—四個過橋人 59
第3章 鎖相環(huán)為什么能夠跟蹤相位 61
3.1 鎖相環(huán)的組成 62
3.1.1 關注信號的相位分量 62
3.1.2 VCO是一個積分器件 63
3.1.3 正弦鑒相器還是余弦鑒相器 65
3.1.4 環(huán)路濾波器的作用 68
3.2 從負反饋電路理解鎖相環(huán) 69
3.2.1 反饋電路的概念 69
3.2.2 負反饋電路的控制作用 70
3.2.3 鎖相環(huán)與基本負反饋電路的區(qū)別 71
3.2.4 分析鎖相環(huán)的工作狀態(tài) 72
3.3 最簡單的鎖相環(huán) 73
3.3.1 一階鎖相環(huán)的SystemView模型 73
3.3.2 確定VCO輸出的同相支路 74
3.4 鎖相環(huán)的基本性能參數(shù) 77
3.4.1 捕獲及跟蹤過程 77
3.4.2 環(huán)路的基本性能要求 78
3.5 分析一階環(huán)的基本參數(shù) 79
3.5.1 數(shù)學方法求解一階環(huán) 79
3.5.2 圖解法分析一階環(huán)工作過程 81
3.5.3 工程設計與理論分析的差異 82
3.5.4 遺忘的參數(shù)——鑒相濾波器截止頻率 85
3.6 小結——千條路與磨豆腐 87
第4章 一階鎖相環(huán)的FPGA實現(xiàn) 89
4.1 一階環(huán)的數(shù)字化模型 90
4.1.1 工程實例需求 90
4.1.2 數(shù)字鑒相器 91
4.1.3 數(shù)控振蕩器 92
4.1.4 計算環(huán)路增益 94
4.2 數(shù)字鑒相濾波器設計 95
4.2.1 FIR與IIR濾波器 95
4.2.2 MATLAB濾波器函數(shù) 97
4.2.3 FIR濾波器的MATLAB設計 100
4.2.4 量化濾波器系數(shù) 102
4.3 Verilog HDL代碼風格 105
4.3.1 文件接口聲明 105
4.3.2 變量的命名方式 106
4.3.3 模塊對齊方式 106
4.3.4 阻塞賦值和非阻塞賦值 107
4.3.5 注釋語句 107
4.4 一階環(huán)的Verilog HDL設計 108
4.4.1 新建FPGA工程 108
4.4.2 數(shù)字乘法器設計 110
4.4.3 低通濾波器設計 112
4.4.4 數(shù)控振蕩器設計 115
4.4.5 頂層文件設計 115
4.5 一階環(huán)的ModelSim仿真測試 119
4.5.1 MATLAB生成測試數(shù)據(jù) 119
4.5.2 編寫測試激勵文件 120
4.5.3 環(huán)路為什么不能鎖定 122
4.5.4 繼續(xù)仿真分析環(huán)路性能 125
4.6 小結—科學的方法 127
第5章 從線性方程到環(huán)路模型 129
5.1 線性時不變系統(tǒng) 130
5.1.1 線性系統(tǒng)的概念 130
5.1.2 時不變系統(tǒng)的概念 132
5.1.3 為什么研究線性時不變系統(tǒng) 132
5.2 信號的線性分解 133
5.2.1 信號的常用分解方法 133
5.2.2 分析的化身—歐拉 135
5.2.3 “e”是一個函數(shù)的極限 137
5.2.4 泰勒、麥克勞林與牛頓 139
5.2.5 上帝創(chuàng)造的公式—歐拉公式 141
5.3 從傅里葉級數(shù)到Z變換 142
5.3.1 溫室效應的發(fā)現(xiàn)者—傅里葉 142
5.3.2 傅里葉級數(shù)是一篇美妙的樂章 143
5.3.3 負頻率信號是什么信號? 147
5.3.4 傅氏變換與拉氏變換 151
5.3.5 Z變換—離散時間系統(tǒng)分析工具 153
5.3.6 如何判斷系統(tǒng)是否穩(wěn)定 156
5.4 鎖相環(huán)路的模型 158
5.5 小結—喬布斯的演講 160
第6章 環(huán)路濾波器決定鎖相環(huán)特性 163
6.1 最簡單的環(huán)路濾波器—RC濾波器 164
6.1.1 RC低通濾波器的頻率特性 164
6.1.2 二階環(huán)路的傳輸函數(shù) 166
6.2 回顧二階線性電路 167
6.2.1 二階線性電路與鎖相環(huán) 167
6.2.2 固有振蕩頻率與阻尼系數(shù) 168
6.2.3 單位階躍信號的響應分析 169
6.3 RC濾波器二階環(huán)的SystemView仿真 172
6.3.1 RC濾波器鎖相環(huán)路模型 172
6.3.2 鎖定狀態(tài)與阻尼系數(shù)的仿真 174
6.4 反饋環(huán)路的穩(wěn)定性分析 177
6.4.1 系統(tǒng)穩(wěn)定與鎖相環(huán)穩(wěn)定的關系 177
6.4.2 頻率特性與環(huán)路的穩(wěn)定性關系 177
6.4.3 伯德圖分析方法 179
6.4.4 伯德圖分析RC二階環(huán)路的穩(wěn)定性 180
6.4.5 二階環(huán)路的相位滯后是如何產生的 181
6.4.6 鑒相濾波器的影響 182
6.5 無源比例積分濾波器 184
6.5.1 頻率特性 184
6.5.2 環(huán)路的傳輸函數(shù) 185
6.5.3 環(huán)路穩(wěn)定性分析及參數(shù)設計 186
6.5.4 環(huán)路的SystemView仿真 188
6.6 有源比例積分濾波器 189
6.6.1 頻率特性 189
6.6.2 環(huán)路的傳輸函數(shù) 191
6.6.3 環(huán)路穩(wěn)定性分析及參數(shù)設計 193
6.6.4 環(huán)路的SystemView仿真 194
6.6.5 為什么穩(wěn)態(tài)相差可以為零 196
6.7 小結—世界上最容易的事 198
第7章 二階環(huán)的FPGA實現(xiàn) 199
7.1 依據(jù)模擬環(huán)設計數(shù)字環(huán) 200
7.1.1 從模擬到數(shù)字——雙線性變換 200
7.1.2 環(huán)路濾波器的數(shù)字化 202
7.1.3 理想二階環(huán)的參數(shù)設計 203
7.1.4 理想二階環(huán)的Verilog HDL設計 205
7.2 FPGA實現(xiàn)后的仿真測試 208
7.2.1 環(huán)路增益對鎖定性能的影響 208
7.2.2 頻差對鎖定性能的影響 210
7.2.3 環(huán)路捕獲范圍測試 211
7.3 理想二階環(huán)的數(shù)字化 213
7.3.1 NCO的數(shù)字化模型 213
7.3.2 環(huán)路的數(shù)字化模型 214
7.4 模擬與數(shù)字環(huán)路的關聯(lián) 215
7.4.1 確定環(huán)路濾波器系數(shù) 215
7.4.2 增益與環(huán)路濾波器系數(shù)的關系 216
7.4.3 兩種系數(shù)計算方法比較 216
7.5 小結—芝諾與莊子的哲學 217
第8章 鎖相環(huán)的性能分析 219
8.1 捕獲性能 220
8.1.1 捕獲過程 220
8.1.2 捕獲帶與捕獲時間 221
8.1.3 輔助捕獲方法 222
8.2 跟蹤性能 224
8.2.1 環(huán)路的穩(wěn)態(tài)相差 224
8.2.2 環(huán)路的頻率特性 225
8.2.3 調制跟蹤與載波跟蹤 228
8.2.4 兩種跟蹤方式的SystemView仿真 229
8.3 噪聲性能 237
8.3.1 噪聲情況下的環(huán)路模型 237
8.3.2 輸出相位噪聲方差 240
8.3.3 環(huán)路噪聲帶寬 241
8.3.4 環(huán)路信噪比 242
8.4 理想二階環(huán)設計公式 244
8.5 小結—興趣是最好的老師 245
第9章 鎖相環(huán)解調PSK信號的FPGA實現(xiàn) 247
9.1 PSK調制解調原理 248
9.1.1 PSK調制原理及信號特征 248
9.1.2 PSK信號的MATLAB仿真 249
9.1.3 鎖相環(huán)解調PSK原理 252
9.2 鎖相環(huán)路解調參數(shù)設計 254
9.2.1 總體性能參數(shù)設計 254
9.2.2 下變頻乘法器設計 256
9.2.3 下變頻低通濾波器設計 257
9.2.4 鑒相乘法器設計 259
9.2.5 數(shù)控振蕩器設計 260
9.2.6 環(huán)路濾波器設計 261
9.3 鎖相解調環(huán)的Verilog設計 262
9.3.1 頂層文件的Verilog設計 262
9.3.2 鑒相器的Verilog設計 264
9.3.3 環(huán)路濾波器的Verilog設計 265
9.4 鎖相解調環(huán)的仿真測試 266
9.4.1 環(huán)路捕獲范圍測試 266
9.4.2 NCO更新周期對環(huán)路增益的影響 267
9.5 小結—漁王的兒子 272
參考文獻 274
2100433B
本書從工程應用的角度詳細闡述鎖相環(huán)技術的工作原理,利用MATLAB及System View仿真工具軟件討論典型電路的工作過程。以Altera公司的FPGA為開發(fā)平臺,以Verilog HDL語言為開發(fā)工具,詳細闡述鎖相環(huán)技術的FPGA實現(xiàn)原理、結構、方法,以及仿真測試過程和具體技術細節(jié),主要包括設計平臺及開發(fā)環(huán)境介紹、鎖相環(huán)跟蹤相位的原理、FPGA實現(xiàn)數(shù)字信號處理基礎、鎖相環(huán)路模型、一階環(huán)路的FPGA實現(xiàn)、環(huán)路濾波器與鎖相環(huán)特性、二階環(huán)路的FPGA實現(xiàn)、鎖相環(huán)路性能分析、鎖相測速測距的FPGA實現(xiàn) 。
可以一樣可以不一樣,有時投標文件會比招標文件多,但內容必須都是招標文件要求提供的內容。
鎖相環(huán)鎖定頻率和相位是怎樣的一個過程 1,看圖中,當△w為0時,鑒相器才會有直流輸出,但鎖相環(huán)沒有
反饋控制
VPN功能說簡單一點,就是使用VPN技術在互聯(lián)網(wǎng)上搭建一條供自己專用的網(wǎng)絡通道, 通過對傳輸?shù)臄?shù)據(jù)進行加密和解密,就像當是在互聯(lián)網(wǎng)上建立了一條自己專用的隧道一樣。 &nb...
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鎖相同步技術是保障并網(wǎng)裝置正常運行的一個重要因素,本文綜述了當前主要的單相鎖相環(huán)系統(tǒng)及其控制。結合三相鎖相環(huán)的控制方法,對幾種常見的鑒相器改進方案,如虛擬乘法器鑒相、微分法構造虛擬兩相鑒相及FIR構造虛擬兩相鑒相法,進行了理論分析、MATLAB建模、仿真分析,并基于DSP實驗平臺進行了實驗驗證。
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針對石油化工野外生產中廣泛使用的直流電動閥設計控制系統(tǒng)。采用光電編碼器檢測電機的角速度和位移,利用數(shù)字信號處理器(DSP)構成數(shù)字鎖相環(huán)(DSPLL),產生控制邏輯,調節(jié)PWM開關頻率和占空比,改變電動機輸入電壓和電流,實現(xiàn)電動閥門開閉控制。系統(tǒng)能夠根據(jù)閥門開閉位置、轉速快慢、轉矩大小,自動調節(jié)轉速快慢和電機拖動轉矩,確保電機轉速、轉矩最佳匹配。用ZY8024-200電機進行試驗,結果證明控制系統(tǒng)響應速度快,精度高,系統(tǒng)諧波和文波幅度小;在轉矩不斷變化時,自動適應轉矩變化,實現(xiàn)了直流電機保護功能。基于DSP鎖相環(huán)的電動閥控制方案,特別適合于石油化工生產中野外直流供電的電動閥控制。
S 頻段頻率合成器要求直接輸出微波信號 , 同時具備寬頻帶 、小步進和低相噪的特點 。要實現(xiàn)這一目標 , 可供選擇的方案有很多種 , 比如 DDS +PLL +正交調制 、單一鎖相環(huán) 、多級鎖相環(huán)等頻率合成方法 ,考慮到成本等因素 ,選擇單片集成鎖相環(huán)方案 。從上述分析可以看出 ,單一整數(shù)鎖相環(huán)無法實現(xiàn)微波頻率下小步進的頻率合成 , 故選擇基于小數(shù)分頻單片集成鎖相環(huán)合成方案 , 最終采用鎖相環(huán)頻率合成器件 LM X2541LQ2380E ?。
1 LMX2541 器件介紹LMX2541 是一款超低噪聲鎖相頻率合成器 ,它內部集成了高性能 ∑-Δ小數(shù)鎖相環(huán)和壓控振蕩器 。與其他通用頻率合成芯片相比 , 它具有以下幾個特點 : ①外圍電路簡單 , 電路體積非常小 ,功耗極低 ,它將前置分頻器 、環(huán)路濾波器 、VCO 和電荷泵都集成在芯片內 ,只需增加少量外圍元件即可完成頻率合成功能 ,電路結構得以簡化 , 在3 . 3 V 電壓供電時 ,全芯片工作峰值電流僅為 204 m A ; ②由于該芯片已將鎖相環(huán) 、環(huán)路濾波器和 VCO 全部集成在一起 ,因此電路的實現(xiàn)難度大大降低 ,只需對寄存器寫入正確的數(shù)據(jù)即可, 電路易于調試 ; ③LM X2541 具有較寬的頻率覆蓋范圍 1 990 ~ 4 000 M H z ,它分為很多頻段 , 每個頻段對應一種型號的 LMX2541 ;④LMX2541 提供了靈活的編程空間 , 在 LM X2541中已經內置了二階 RC 低通濾波器 , 可以滿足一般要求 ,用戶可以根據(jù)需要定義更高階數(shù)的 RC 低通濾波 器的 參 數(shù)來 獲得 更 高質 量的 信 號 ; ⑤在LM X2541 中還定義了抖動控制的寄存器 , 可以選擇強抖動 、弱抖動和不抖動 3 種工作模式 ,可以有效地改善信號的相位噪聲特性并抑制雜散 。
2 頻率合成器硬件結構頻率合成器硬件結構包括 : 鎖相環(huán)模塊 、微控制器 、低噪聲電源等主要部分組成 。鎖相環(huán)模塊由LM X2541和環(huán)路濾波器組成 。
鎖相環(huán)模塊是頻率合成的核心部分 ,內部配置了 100 M H z 的壓控晶體振蕩器 VCXO ,也可以從外部輸入更精準的參考源信號 。微控制器實現(xiàn)人機接口 , 接收外部輸入的信號頻率 、幅度等參數(shù) , 針對LM X2541 器件進行頻率合成優(yōu)化計算 , 產生頻率 、幅度控制字 , 并將控制字通過 M icrowire 總線寫入LM X2541 內部寄存器 。低噪聲電源產生 LM X2541所需的 +3 . 3 V 直流電壓 ?。
3 環(huán)路濾波器參數(shù)設計采用 Natio n ClockDesign Too l( NCDT )時鐘設計工具軟件對頻率合成器進行設計優(yōu)化 , 由于選用的 LM X2541 是全鎖相環(huán)器件 ,因此優(yōu)化設計主要工作是環(huán)路濾波器的參數(shù)選取 。
S 頻段頻率合成器輸出頻率范圍設定為 2 200 ~2 300 MH z , 頻率分辨率為 10 kH z ,通過 NCDT 軟件優(yōu)化分析 ,采用 4 階 RC 濾波器作為環(huán)路低通濾波器 。
4 環(huán)路雜散抑制技術
小數(shù) N 分頻鎖相環(huán)雜散主要由分頻控制電路產生 ,分頻控制電路形成有規(guī)律的控制信號 ,同時也就產生了有規(guī)律的雜散 ,小數(shù) N 分頻鎖相環(huán)第一雜散位置出現(xiàn)在 f PD /Fden 。由于小數(shù)分頻鎖相環(huán)雜散形成的規(guī)律性 ,因此可以通過打破這一規(guī)律來抑制雜散的形成 。 LM X2541 內部通過 ∑-Δ 調制技術和分頻控制抖動相結合來抑制小數(shù)分頻所產生的雜散 ?。
1) 傳統(tǒng)小數(shù)分頻控制范圍為 N IN T ~ N INT +1 ,有 2 個分頻控制字 ,等效于一階 ∑-Δ 調制 ; 二階 ∑-Δ調制控制范圍為 N IN T -1 ~ N IN T +2 , 有 4 個分頻控制字 ; 三階 ∑-Δ 調制控制范圍為 N INT -3 ~N IN T +4 , 有 8 個分頻控制字 ; 四階 ∑-Δ 調制控制范圍為 N IN T -7 ~ N IN T +8 , 有 16 個控制字 。 ∑-Δ調制技術相當于將雜散頻帶展寬 ?。
2) 分頻控制抖動技術是改變傳統(tǒng)分頻的控制規(guī)律 ,將分頻控制字作隨機化處理 ,這一處理相當于將原先集中的雜散頻率附近的功率平均分布到展寬后的頻率范圍內 ,因而可以明顯降低雜散電平 。微控制器對 LM X2541 寄存器編程設置 ∑-Δ調制的階數(shù)和抖動控制 , 可以實現(xiàn)對輸出信號的雜散抑制 ?。
5 頻率合成器相位噪聲測試微控制器根據(jù)輸出頻率 、幅度 、濾波器和環(huán)路控制等其他參數(shù),計算得出 LM X2541 寄存器控制字,通過 I/O 口模擬 Microw ire 總線讀寫時序將控制字寫入 LMX2541 內部寄存器 ,用 H P8563E 頻譜分析儀測試頻率合成器輸出信號。頻 率合 成 器的 相 位測 試結 果 表明 , 基 于LM X2541 的 S 頻段頻率合成器輸出信號表現(xiàn)出良好的相位噪聲特性 ?。
第1 章 FPGA 架構總體設計 ········································································· 1
1.1 FPGA 芯片研制流程·········································································· 1
1.2 FPGA 架構設計流程·········································································· 7
1.3 FPGA 規(guī)模和資源劃分 ····································································· 17
1.4 FPGA 中功能模塊劃分 ····································································· 20
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第2 章 FPGA 中時鐘網(wǎng)絡 ·········································································· 30
2.1 簡介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 時鐘網(wǎng)絡設計方法 ·········································································· 43
2.4 時鐘網(wǎng)絡的靈活性 ·········································································· 48
2.5 路由級聯(lián) ······················································································ 51
2.6 仿真實驗 ······················································································ 55
2.7 時鐘網(wǎng)絡熱學建模 ·········································································· 61
2.8 仿真實驗 ······················································································ 62
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第3 章 FPGA 中電源/地線網(wǎng)絡和漏電流 ······················································· 68
3.1 電源/地線網(wǎng)絡 ··············································································· 68
3.2 IR-DROP 分析與優(yōu)化 ········································································ 71
3.3 漏電流組成 ··················································································· 73
3.4 降低漏電流的方法 ·········································································· 74
3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真實驗 ······················································································ 81
3.7 不均勻測試點的IR-DROP 求解 ··························································· 87
3.8 FPGA 電源網(wǎng)絡IR-DROP 分析 ···························································· 89
本章參考文獻 ······················································································ 94
第4 章 FPGA 中可編程邏輯單元 ································································· 98
4.1 基于多路選擇器的邏輯單元 ······························································ 98
4.2 基于四輸入LUT 的可編程邏輯單元的設計 ·········································· 102
4.3 LUT 的模型與實現(xiàn) ········································································ 103
4.4 LUT 的輸入數(shù)目K 的確定 ······························································· 106
4.5 進位邏輯 ····················································································· 109
4.6 基于查找表結構的FPGA 的不足 ······················································· 115
4.7 AIC 結構邏輯簇 ············································································ 117
4.8 基于AIC 結構FPGA 的邏輯簇 ························································· 120
4.9 面向AIC 的映射工具及結構評估平臺 ················································ 124
4.10 結構特征匹配的AIC 簇互連優(yōu)化 ···················································· 125
4.11 仿真分析和比較 ·········································································· 131
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第5 章 FPGA 中可編程I/O 模塊 ································································· 136
5.1 可編程I/O 系統(tǒng)結構 ······································································ 136
5.2 IOE 中的可編程輸入緩沖器設計 ······················································· 138
5.3 IOE 中的可編程輸出緩沖器設計 ······················································· 144
5.4 可編程I/O 的后端版圖設計······························································ 156
5.5 高可靠I/O 模塊的后端版圖與測試 ····················································· 166
5.6 可編程I/O 的供電策略 ··································································· 172
5.7 全芯片IO 的ESD 技術 ··································································· 173
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第6 章 FPGA 中DDR 存儲器接口 ······························································ 182
6.1 DDR SDRAM 芯片的工作原理 ·························································· 182
6.2 FPGA 芯片中DDR 存儲器接口系統(tǒng)設計 ············································· 184
6.3 DDR 存儲器接口控制器的設計和驗證 ················································ 191
6.4 延時鎖相技術 ··············································································· 194
6.5 延時鎖定環(huán)電路的分析與對比 ·························································· 196
6.6 數(shù)字延時鎖定環(huán)電路的性能分析與優(yōu)化 ·············································· 201
6.7 延時鎖定環(huán)線性模型與穩(wěn)定性分析 ···················································· 205
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第7 章 FPGA 中數(shù)字延時鎖定環(huán) ································································ 213
7.1 實現(xiàn)相移的全數(shù)字延遲鎖定環(huán) ·························································· 213
7.2 數(shù)字控制延時鏈 ············································································ 215
7.3 時間數(shù)字轉換器 ············································································ 220
7.4 雙向移位計數(shù)器 ············································································ 221
7.5 鑒相器與鎖定邏輯 ········································································· 222
7.6 延遲鎖定環(huán)的版圖設計 ··································································· 224
7.7 延遲鎖定環(huán)環(huán)路的仿真 ··································································· 224
7.8 芯片的物理實現(xiàn)與測試平臺 ····························································· 225
7.9 DDR 接口的數(shù)據(jù)通路的測試驗證 ······················································ 227
7.10 數(shù)字延時鎖定環(huán)的測試 ································································· 229
7.11 數(shù)字占空比矯正電路的測試 ···························································· 232
本章參考文獻 ····················································································· 234
第8 章 FPGA 中連線連接盒 ······································································ 236
8.1 引言 ··························································································· 236
8.2 問題分析 ····················································································· 237
8.3 利用模擬退火算法優(yōu)化CB 拓撲結構 ·················································· 241
8.4 實驗及結果分析 ············································································ 246
8.5 連線開關盒的電路結構設計方法 ······················································· 251
本章參考文獻 ····················································································· 259
第9 章 FPGA 中互連線段長度分布 ····························································· 261
9.1 所提優(yōu)化方法的基本思路 ································································ 261
9.2 以面積延時積最小為目標的優(yōu)化 ······················································· 265
9.3 針對所提優(yōu)化方法的討論 ································································ 268
9.4 設計實驗 ····················································································· 269
9.5 FPGA 芯片的設計實現(xiàn) ···································································· 270
9.6 芯片的測試準備 ············································································ 272
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第10 章 FPGA 中的配置模塊 ···································································· 277
10.1 配置系統(tǒng)的基本組成及特點 ···························································· 277
10.2 配置系統(tǒng)的功能需求 ···································································· 279
10.3 配置系統(tǒng)的硬件結構分析 ······························································ 281
10.4 配置碼流協(xié)議的結構及其對配置系統(tǒng)的影響 ······································· 286
10.5 配置系統(tǒng)總體框架 ······································································· 292
10.6 配置碼流協(xié)議的設計 ···································································· 297
10.7 配置系統(tǒng)的電路設計與實現(xiàn) ···························································· 300
10.8 配置系統(tǒng)采用的驗證工具與方法 ······················································ 305
10.9 配置系統(tǒng)的驗證方案與功能點的抽取 ················································ 310
10.10 配置系統(tǒng)功能驗證平臺的設計 ······················································· 312
10.11 配置系統(tǒng)驗證結果 ······································································ 319
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杜勇,四川省廣安市人,高級工程師。1999年于湖南大學獲電子工程專業(yè)學士學位,2005年于國防科技大學獲信息與通信工程專業(yè)碩士學位。主要從事數(shù)字信號處理、無線通信以及FPGA應用技術研究。發(fā)表學術論文十余篇,出版《數(shù)字濾波器的MATLAB與FPGA實現(xiàn)(第2版)》、《數(shù)字通信同步技術的MATLAB與FPGA實現(xiàn)》、《數(shù)字調制解調技術的MATLAB與FPGA實現(xiàn)》等多部著作。